(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a structure and method for making contact openings for embedded dynamic random access memory (DRAM) circuits. The structure and process are particularly useful for making contact openings in an insulating layer to the top electrode of the DRAM capacitor with low contact resistance, while concurrently etching contact openings to the substrate for bit-line contact openings and for contact openings to the logic areas without overetching the contact areas which would otherwise result in high leakage currents.
(2) Description of the Prior Art
Integrated logic and DRAM structures, also referred to as embedded memory, are becoming increasingly important for future product applications. These advanced circuits require field effect transistors (FETs) with shallower diffused junctions in logic areas to improve performance, while forming DRAM capacitors having reduced size and low-electrical-contact resistance to the top electrode. However, when a single masking step is used, it is difficult to make contacts to shallow diffused junctions for the FETs without overetching, while concurrently forming low-electrical-resistance contacts to the DRAM capacitor. This problem for a conventional (prior-art) logic/DRAM integrated structure using stacked capacitors is best described with reference to FIG. 1, in which the logic area is shown on the left (labeled Logic), and the DRAM area with stacked capacitors is depicted on the right (labeled DRAM). A typical structure consists of a semiconductor substrate 10 in which shallow trench isolation 12 is formed to electrically isolate the device areas. FETs are formed by growing a gate oxide 16, and by depositing a polysilicon layer and patterning to form gate electrodes 18. Lightly doped drains 24 are implanted, sidewall spacers 22 are formed on the gate electrodes, and another implant is used to form the source/drain contact areas 25. A metal silicide is then used, such as in a salicide process, to make contacts 26 to the gate electrodes 18, to the shallow source/drain contact areas 25, and bit-line contacts, also labeled 25, in the DRAM area. Next, a planar insulating layer 28 is formed over the FETs. Storage node contacts 30 are formed in the insulating layer 28 for capacitor bottom electrodes 32 in the DRAM area. The capacitors are completed by depositing sequentially an interelectrode dielectric layer 34, depositing a conducting layer for top electrodes 36, and forming an anti-reflective coating (ARC) 38, and patterning. A second insulating layer 40 is then deposited and planarized over the capacitors. More specifically, the problem arises when a single mask is used to etch the contact openings 1 of varying depths to the shallow diffused junctions 25 and through the ARC 38 to the capacitor top electrodes 36. In order to etch through the ARC 38 at the region R in opening 1 for low contact resistance, the shallow diffused junctions 25 can be overetched resulting in high-leakage currents. The conventional process that utilizes two separate masking and etching steps is not cost-effective and can cause alignment problems on integrated circuits having 0.1 micron (um) minimum feature sizes.
This problem also arises for conventional trench capacitors as depicted in FIG. 2. In FIG. 2 the RAM cell region is depicted on the left, and the logic region is depicted on the right. In this approach shallow trench isolation 12 is formed in a substrate 10. FET devices are formed similar to the process for making the logic/DRAM structures having stacked capacitors. In this approach, the trench capacitors are formed by recessing the STI 12, and forming bottom electrodes 104 in the recesses. Next, a stacked layer composed of an interelectrode dielectric layer 106, a conducting layer 108, and an anti-reflective coating (ARC) 110 is deposited. The stacked layer is patterned to form the top electrodes 108, having the ARC 110 on the surface, for the trench capacitors. Then an insulating layer 114 is deposited and planarized. Next, a single mask and etching step are used to form contact openings 116 of varying depths to make contact to the diffused junctions 25, to the gate electrodes 18, and to the capacitor top electrodes 108. However, when the contact openings 116 are etched down to the shallow diffused junctions 25, the contact opening etched to the capacitor top electrode is not completely etched through the ARC 110, resulting in high contact resistance, as indicated by the point R in FIG. 2. If the contact openings 116 are etched through the ARC 110 to make good ohmic contact, the contact openings 116 to the shallow diffused junctions 25 are overetched resulting in damage (high-leakage currents).
Several methods for making contact openings to capacitors for logic/DRAM circuits have been reported in the literature. For example, in U.S. Pat. No. 6,403,417 B1 to Chien et al., a method is described for making via holes and strip contact holes for embedded memory. In their approach the via holes and the contact holes are formed separately in the dielectric layer. Chien et al. are silent about using a single masking step. In U.S. Pat. No. 6,485,988 B2 to Ma et al., a method is described for using a hydrogen-free contact etch for ferroelectric capacitor formation. Ma et al. are also silent about using a single masking step for forming contact openings to varying depths.
However, there is still a need in the semiconductor industry to provide a process for making logic circuits with embedded DRAM devices using a single mask for etching contact openings of varying depths without resulting in high contact resistance to capacitor top electrodes and high leakage currents to shallow diffused junctions on/in the substrate surface.